
`timescale 1ns / 1ns
module SpiTransmitterTest  ; 

  wire  oSclk   ; 
  wire  [7:0]  oData   ; 
  wire  oCs   ; 
  reg   iMiso   ; 
  wire  oBusy   ; 
  reg   iStart   ; 
  reg  [7:0]  iData   ; 
  wire   oMosi   ; 
  reg    iClk   ; 
  SpiTransmitter  DUT  ( 
      .oSclk (oSclk ) ,
      .oData (oData ) ,
      .oCs (oCs ) ,
      .iMiso (iMiso ) ,
      .oBusy (oBusy ) ,
      .iStart (iStart ) ,
      .iData (iData ) ,
      .oMosi (oMosi ) ,
      .iClk (iClk ) ); 



// "Clock Pattern" : dutyCycle = 50
// Start Time = 0 ns, End Time = 1 us, Period = 20 ns
  initial
  begin
	  iClk  = 1'b0  ;
    repeat(100)
    begin
	  #10  iClk  = 1'b1  ;
	  #10  iClk  = 1'b0  ;
    end
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 1 us, Period = 0 ns
  initial
  begin
	  iMiso  = 1'b0  ;
	  #290  iMiso  = 1'b1  ;
	  #480  iMiso  = 1'b0  ;
	  #240 iMiso  = 1'b1  ;
	  #240 iMiso  = 1'b0  ;
	  #240 iMiso  = 1'b1  ;
	  #240 iMiso  = 1'b0  ;
	 # 300 ;
// dumped values till 1 us
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 1 us, Period = 0 ns
  initial
  begin
	  iData  = 8'b01101010  ;
	 # 2000 ;
// dumped values till 1 us
  end


// "Constant Pattern"
// Start Time = 0 ns, End Time = 1 us, Period = 0 ns
  initial
  begin
	  iStart  = 1'b0  ;
	 # 20	  iStart  = 1'b1  ;
	 # 60	 iStart  = 1'b0  ;
	 # 1920 ;
// dumped values till 1 us
  end

  initial
	#2000 $stop;
endmodule
